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Development of an Improved Frame Level Redundancy Scrubbing Algorithm for Static Random Access Memory Based Field Programmable Gate Array

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Development of an Improved Frame Level Redundancy Scrubbing Algorithm for Static Random Access Memory Based Field Programmable Gate Array.

Abstract

The use of Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance.

However, SRAM-based fpgas are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design.

This research presents the development of an improved Frame Level Redundancy (FLR) Scrubbing algorithm for SRAM-based FPGA to mitigate against radiation-induced SEU.

The improved FLR uses Cyclic Redundancy Check (CRC) as an error detection technique to enable configuration memory scrubbing as a solution to mitigate SEU through upset detection and correction.

Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU.

The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB r2013a.

The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics.

The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.

Introduction

Background of the study

Static random access memory (sram) based field programmable gate arrays (fpgas) are complementary metal oxide semiconductor (cmos) devices with special characteristic of re-configurability making them desirable for use in systems with evolving technology (jorge et al., 2015).

The use of fpgas have been shown to provide high computational density and efficiency for many computing applications by allowing circuits to be customized to any application of interest (wirthlin, 2015).

They are attractive to critical applications due to their high performance, power consumption, and reconfiguration capability (tonfat et al., 2015), and can be re-configured in the field, design updates can be performed while the device is still operational (kastensmidt & rech, 2016).

Compared to application specific integrated circuits (asics), whose functions cannot be altered after fabrication, sram-based fpgas have the advantage of being reprogrammed and providing a lower cost per device in small quantities (li, 2012), therefore, there is great interest in exploiting these benefits in space and other radiation environments (wirthlin, 2015).

Configurable fpgas are better alternative for application specific processing in space based applications because of their flexibility and in-system re-programmability; also fpgas are versatile devices that allow a function to be implemented by mapping it into the fpga’s pre-existing logic resources.

The mapping is referred to as its configuration (berg et al., 2008).In sram based fpgas, the mapped circuit is totally controlled by the configuration memory, which is composed of sram cells (reorda et al., 2005).

A modern generation fpga have tens of thousands to millions System logic gates, with hundreds of millions of configuration bits, dominating the sram cells in the device (jing et al., 2015).

Similar to memory devices, fpgas have high density of transistors and interconnect wires (stott et al., 2008).

References

 Aishwarya, S., & Mahendran, G. (2016). Multiple Bit Upset correction in SRAM based FPGA using self repairable Erasure codes. Paper presented at the International Conference on Emerging Engineering Trends and science (ICEETS-2016), 356- 362.

Akagic, A., & Amano, H. (2012). Performance analysis of fully-adaptable CRC accelerators on an FPGA. Paper presented at the 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), 575-578.

Akagic, A., & Amano, H. (2012). A study of adaptable co-processors for cyclic redundancy check on an FPGA. Paper presented at the 2012 International Conference on Field-Programmable Technology (FPT), 119-124.

Akagić, A., & Amano, H. (2011). High speed CRC with 64-bit generator polynomial on an FPGA. ACM SIGARCH Computer Architecture News, 39(4), 72-77.

Alagoz, B. B. (2009). Hierarchical Triple-Modular Redundancy (H-TMR) Network For Digital Systems. arXiv preprint arXiv:0902.0241, 1-15.

Asadi, H., Tahoori, M. B., Mullins, B., Kaeli, D., & Granlund, K. (2007). Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems. IEEE Transaction on Nuclear Science, 54(6), 2714-2726.

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