Tag: formal verification vlsi

Formal Verification of a Network on Chip

Formal Verification of a Network on Chip. ABSTRACT Current advancement in VLSI technology allows more circuit to be integrated on a single chip forming a System on Chip (SoC). The state of art in on-chip intermodule connection of using a shared bus with a Common arbiter poses scalability problems and become a performance bottleneck as […]

Continue Reading »